The present invention relates to a memory data holding circuit which, in case of power supply interruption, supplies an operating current from a backup power supply to a memory to retain its stored data.
A device using a memory is sometimes provided with a data holding circuit which, in case of power source interruption, supplies an operating current from a backup power supply to the memory, preventing destruction of its stored data.
FIG. 5 illustrates in block form an example of a conventional data holding circuit. Reference numeral 1 indicates a memory such as a C-MOS-RAM or the like, 2 a power supply unit which supplies an operating voltage V.sub.CC to each part of the device and yields a detecting signal a which goes to a "1" in the power-ON state and a "0" in the power-OFF state, 3 a backup power supply, 4 a changeover switch which is connected to the side of a contact A or B depending upon whether the detecting signal a is at the "1" or "0" level, 5 an AND gate and 6 an input terminal for a chip select signal b. Incidentally, the detecting signal a goes to the "1" state a certain elapsed time after the rise of the operating voltage V.sub.CC and goes to the "0" state a certain time before the fall of the operating voltage V.sub.CC. The memory 1 is accessible when the chip select signal b is at the "1" level which is applied via the AND gate 5.
While the operating voltage V.sub.CC is supplied to each part of the device from the power supply unit 2, the detecting signal a is at "1", so the changeover switch 4 will be connected to the contact A side, through which the operating voltage V.sub.CC is provided to the memory 1. Furthermore, since the AND gate 5 is in the ON state in this instance, the chip select signal b will be applied via the AND gate 5 to the memory 1. Moreover, when the power supply is turned OFF, the detecting signal a goes to a "0", so the changeover switch 4 is connected to the contact B side and the backup power supply 3 will provide an operating current to the memory 1, holding its stored contents.
With a view to preventing access to the memory 1 during the power-OFF period, however, the conventional arrangement shown in FIG. 5 is adapted so that the chip select signal b is applied to the memory 1 via the AND gate 5 which is controlled by the detecting signal a. This introduces a defect as follows: That is, if power is disconnected from the device when the chip select signal b is at "1" and data is being written in the memory 1, the AND gate 5 will be turned OFF to discontinue the access to the memory 1 although data is being written therein, so that the contents stored at an address being accessed at that time may sometimes become inidentifiable.